I have to implement a circuit that performs A+B+C+D serially. A and B are added using the first adder, the result is added to C using the second adder and finally the result is added to D using the third adder, one after the other. The problem is, in order to make the design low power. I have to turn off the other two adders which are not in use.

All I can think is Enable and Disable signals, but this causes latency issues. How do I synthesize this in in an effective manner in verilog?

A,B,C,D may change every clock cycle. A start signal is used to indicate when a new calculation is required. I assume your adder has been implied via sum = A + B.

Circuit

Adder Verilog Code

For area optimisation why do you not share a single adder unit. A+B in CLK1, SUM+C in CLK2, SUM+D in CLK3. Then you have nothing to disable or clock gate. The majority of power is used when values change, so zeroing inputs when not used can actually increase power by creating unnecessary toggles. As adders are combinatorial logic all we can do to save power for a given architecture is hold values stable, this could be done through the use of clock gate cells controlling/sequencing input and output flip-flops clks. Update With the information that a new calculation may be required every clock cycle, and there is an enable signal called start.

Th question made reference to adding them serially ie: sum1 = A + B; sum2 = sum1 + C; sum3 = sum2 + D; Since the result is calculated potentially every clock cycle they are all on or all off. The given serialisation (which is all to be executed in parallel) has 3 adders stringed together (ripple path of 3 adders).

If we refactor to: sum1 = A + B; sum2 = C + D; sum3 = sum1 + sum2; Or ripple path is only 2 adders deep allowing a quicker settling time, which implies less ripple or transients to consume power. I would be tempted to do this all on 1 line and allow the synthesis tool to optimise it.

Sum3 = A + B + C + D; For power saving I would turn on auto clock gating when synthesising and use a structure that worked well with this technique: always @(posedge clk or negedge rstn) begin if (rstn) begin sum3.

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